By John M. Cohn, David J. Garrod, Visit Amazon's Rob A. Rutenbar Page, search results, Learn about Author Central, Rob A. Rutenbar, , L. Richard Carley
This e-book offers an in depth precis of study on computerized format of device-level analog circuits that was once undertaken within the past due Eighties and early Nineties at Carnegie Mellon collage. We specialise in the paintings at the back of the construction of the instruments referred to as KOAN and ANAGRAM II, which shape a part of the middle of the CMU ACACIA analog CAD approach. KOAN is a tool placer for customized analog cells; ANANGRAM II an in depth zone router for those analog cells. we attempt to give the motivations in the back of the structure of those instruments, together with particular dialogue of the delicate know-how and circuit matters that needs to be addressed in any profitable analog or mixed-signal structure device. Our strategy in organizing the chapters of the publication has been to provide our algo rithms as a sequence of responses to those very actual and intensely tough analog structure difficulties. eventually, we current a variety of examples of effects generated through our algorithms. This study was once supported partly through the Semiconductor learn Corpora tion, through the nationwide technological know-how starting place, by means of Harris Semiconductor, and through the foreign enterprise Machines company Resident learn software. ultimately, only for the list: John Cohn was once the dressmaker of the KOAN placer; David Garrod used to be the fashion designer of the ANAGRAM II router (and its predeces sor, ANAGRAM I). This booklet used to be architected through all 4 authors, edited through John Cohn and Rob Rutenbar, and produced in comprehensive shape through John Cohn.
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Additional info for Analog Device-Level Layout Automation
This Section describes the basic digital-style placement functionality which underlies the full KOAN placer. At this level, the goal of the placer is merely to arrange generated devices available in several variants such that the estimated interconnect length and total layout area are minimized. We must also guarantee that the layouts are free of design-rule errors and have sufficient inter-device space to allow for routing. The discussion below is geared towards describing algorithmically how these first-order placement goals are achieved in terms of the placer's representation, move-set, cost-function, and annealing schedule.
Also, unlike slicing placement, flat placement imposes 1 Note: self-symmetry refers to devices which straddle the global symmetry line. :a Global placement flow revisited. no restriction on the relative position of devices. This allows better device packing, and thus better layout density, particularly in the case when a circuit contains a mix of device sizes. There is also a third advantage to flat placement. The fact that devices are able to overlap in the course of placement evolution allows us to explore the possibility of beneficial legal device overlaps, in which two devices are allowed to share common geometry.
This is because we treat well connections like all other device connections. Observe also that we rely on the placer itself, rather than on the device generators to create this simplified geometric abstraction. We do this to allow the placer to calculate more accurately the electrically significant area and perimeter of all device terminals. Although the full benefit of our detailed device representation will not become apparent until we discuss device geometry sharing in more detail, it should be clear that the detail of our protection frame representation is more than adequate for the detection and elimination of undesirable device overlap.
Analog Device-Level Layout Automation by John M. Cohn, David J. Garrod, Visit Amazon's Rob A. Rutenbar Page, search results, Learn about Author Central, Rob A. Rutenbar, , L. Richard Carley